verilog实现FIR滤波器方法_升余弦fir滤波器verillog

算法原理参考：https://blog.csdn.net/u014783685/article/details/74466107

module fir_pipeline (
    input clk,
    input rst,
    input signed [15:0] data_in,
    output reg signed [15:0] data_out
);

parameter N = 17; // FIR 滤波器长度
parameter W = 16; // 输入输出信号位宽

reg signed [W-1:0] delay_line [0:N-1]; // 延迟线，存储输入信号
reg signed [W-1:0] coeff [0:N-1] = {16'h0001, 16'h0002, 16'h0003, 16'h0004, // FIR 系数
                                     16'h0005, 16'h0006, 16'h0007, 16'h0008,
                                     16'h0009, 16'h000A, 16'h000B, 16'h000C,
                                     16'h000D, 16'h000E, 16'h000F, 16'h0010,
                                     16'h0011}; 

reg signed [W-1:0] mul_result [0:N-1]; // 乘法结果
reg signed [W-1:0] sum_result; // 加法结果

integer i;

always @(posedge clk or posedge rst) begin
    if (rst) begin
        // 复位操作
        for (i = 0; i < N; i = i + 1) begin
            delay_line[i] <= 0;
            mul_result[i] <= 0;
        end
        sum_result <= 0;
    end else begin
        // 数据流水线
        delay_line[0] <= data_in;
        for (i = 0; i < N; i = i + 1) begin
            if (i == 0) begin
                mul_result[i] <= delay_line[i] * coeff[i];
            end else begin
                mul_result[i] <= delay_line[i] * coeff[i] + mul_result[i-1];
            end
        end
        sum_result <= mul_result[N-1];
        data_out <= sum_result;
    end
end

endmodule

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