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“callback(回调)”机制是一种在不更改实际代码的条件下更改验证组件行为的机制。
class abc_transactor; virtual taskpre_send(); endtask virtual taskpost_send(); endtask task xyz(); this.pre_send(); this.post_send(); endtask : xyz endclass :abc_transactor class my_abc_transactor extend abc_transactor; virtual taskpre_send(); ... //This function is implemented here endtask virtual taskpost_send(); ... //This function is implemented here endtask endclass :my_abc_transactor
factory pattern (工厂模式),旨在解决对象的创建问题。
== Queue(队列)==
package ABC;
typedef enum {RED, GREEN,YELLOW} Color;
void function do_nothing()
endfunction
endpackage : ABC
import ABC::Color;
import ABC::*; // Import everything inside the package
通过$cast可以将值赋给数据类型不同的变量,特别是将基类的句柄赋值给扩展类的句柄;
static casting
i = int'(10.0-0.1); // static cast convert real to integer
== dynamic casting==
function int $cast( singular dest_var, singular source_exp );
task $cast( singular dest_var, singular source_exp );
top-level scope,用于引用任意层次中例化的模块
$root.A; // top level instance A
$root.A.B.C; // item C within instance B within top level instance A
int UniqVal[10];
foreach(UniqVal[i]) UniqVal[i]= i;
UniqVal.shuffle(); //打乱排序
使用forever语句以及fork join_any语句;
always @(posedge clk or negedge reset) begin if(!reset) begin data <= '0; end else begin data <= data_next; end end // Using forever : slightly complex but doable forever begin fork begin @ (negedge reset); data <= '0; end begin @ (posedge clk); if(!reset) data <= '0; else data <=data_next; end join_any disable fork end
modports是interface的一部分,用于指定不同模块接口所连接信号的方向;
interface my_intf;
wire x, y, z;
modport master (input x, y, output z);
modport slave (output x, y, input z);
endinterface
initial begin
clk= 0;
forever#(cycle/2) clk <= ~ clk;
end
typedef class C2;
class C1;
C2 C;
endclass
class C2;
C1 C;
endclass
int x,y,z;
constraint XYZ{
solve x before y;
solve y before z;
solve z before x;
}
covergroup cg;
cover_point_y : coverpoint y ;
cover_point_z : coverpoint z ;
cross_yz : cross cover_point_y,cover_point_z ;
endgroup
disable fork;
interface arb_if(input bit clk);
logic [1:0] grant, request;
logic rst;
property request_2state;
@(posedge clk) disable iff (rst)
$isunknown(request) == 0; //Make sure no Z or X found
endproperty
assert_request_2state: assert property(request_2state);
endinterface
class ABC;
rand bit [7:0] data [];
constraint cc {
data.size inside{[1:10]}; // Constraining size
data[0] > 5; //Constraining individual entry
foreach(data[i]) // All elements
if(i > 0)
data[i]> data[i-1];
}
endclass
randsequence( main )
main : first second done ;
first : add | dec ;
second : pop | push ;
done : { $display(“done”); };
add : { $display(“add”); } ;
dec : { $display(“dec”); } ;
pop : { $display(“pop”); } ;
push : { $display(“push”); };
endsequence
program main; bit [0:2] y; bit [0:2] values[$]= '{3,5,6}; covergroup cg; cover_point_y : coverpoint y { option.auto_bin_max= 4 ; } endgroup cg cg_inst = new(); initial foreach(values[i]) begin y = values[i]; cg_inst.sample(); //gather coverage end endprogram
constraint_mode();
initial begin typedef struct { int a; byte b; shortint c; int d; } my_struct_s; my_struct_s st = '{ 32'haaaa_aaaad, 8'hbb, 16'hcccc, 32'hdddd_dddd }; $display("str = %x %x %x %x ",st.a, st.b, st.c, st.d); end
typedef union {int i; real f; } num_u;
num_u un;
un.f = 0.0; // setvalue in floating point format
class Scoping;
string oname;
function new(string oname);
this.oname = oname; // classoname = local oname
endfunction
endclass
union tagged {
inti;
realr;
} data;
data data_un;
data_un = tagged i 5; //store the5 in data.i, and set it as the implicit tag.
d_out = data_un.i; //read value
d_out = data_un.r;//ERROR:memeber doesnt match the union's implicit tag
class XYZ;
extern void task SayHello();
endclass
void task XYZ :: SayHello();
$Message("Hello !!!\n");
endtask
bit :2值逻辑,默认为0;
logic:4值逻辑,默认为1;
int q[$] = {1,2,3,4};
int index[4], out;
foreach(index[i])
index[i] = i;
index.shuffle(); //orindex[i] = $urandom_range (1,4);
foreach(q[i])
out = q[index[i]];
mailbox 或者 queue
<< 和 >>
==<< ==:从右向左打包数据;
== >> ==:从左向右打包数据;
-检查该对象是否已初始化,在SV中,所有未初始化的对象句柄都具有null值
always_ff @(posedge clk iff rst == 0 or posedge rst)
begin : ADDER
if (rst) begin
sum <= 0;
parity <= 0;
end
else begin
sum <= b + a;
parity <= ^(b + a);
end
end
always_comb
begin
sum = b + a;
parity = ^sum;
end
always_latch
begin : ADDER
if (enable) begin
sum <= b + a;
parity <= ^(b + a);
end
end
int [1:2]a[1:3] = '{'{0,1,2},'{3{4}}};
interface arb_if(input bit clk); logic [1:0] grant, request; logic rst; clocking cb @(posedge clk); // Declare cb output request; input grant; endclocking modport TEST (clocking cb, output rst);//rst is asynchronous signal modport DUT (input request, rst, outputgrant); endinterface module test(arb_if.TEST arbif); initial begin arbif.cb.request <= 0; @arbif.cb; $display("@%0t: Grant =%b", $time, arbif.cb.grant); end endmodule
mailbox mbx;
mbx = new(); // Allocate mailbox
mbx.put (data); //Put data object in mailbox
mbx.get (data); // Data updated with new data from FIFO
count = mbx.num(); // To count number of elements is mailbox
捕获来自随机激励刺激,封装覆盖率要求
enum { red, green, blue } color;
bit [3:0] pixel;
covergroupg1 @ (posedgeclk);
coverpoint color;
coverpoint pixel;
AxC: cross color, pixel;
endgroup
if (!obj.randomize())
begin
$display("Error in randomization");
$finish;
end
或者
assert (!obj.randomize())
property name_of_property;
< test expression > or
< complex sequenceexpressions >
endproperty;
assert_name_of_property: assert property (name_of_property);
x [->4:7]
program automatic test;
task wait for mem(input [31:01 addr, expect data,
output success);
while (bus. addr!== addr)
@(bus . addr);
success = (bus. data== expect data);
endtask
...
endprogram
bit [7:0]b_unpack[3]; // Unpacked
bit [3:0] [7:0]bytes; // 4 bytes packed into 32-bits
bytes =32'hCafe Dada;
bit [3:0] [7:0] barray[31]; // Packed: 3x32-bit
bit [31:0] Iw =32'h0123 4567; // Word
barray[01 = lw;
barray[0][31 =8'h01;
barray[0] [1][61 =1'h1;
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