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Verilog实现4-bit行波进位加法器和超前进位加法器_四位超前进位加法器各进位位并行进位表达式

四位超前进位加法器各进位位并行进位表达式

1. 行波进位实现方式:

  1. module adder4_ripple
  2. (
  3. input wire [3:0] a, b,
  4. input wire Cin0,
  5. output wire [3:0] y,
  6. output wire Cout
  7. );
  8. wire Cin1, Cin2, Cin3;
  9. full_adder1 a1(a[0], b[0], Cin0, y[0], Cin1);
  10. full_adder1 a2(a[1], b[1], Cin1, y[1], Cin2);
  11. full_adder1 a3(a[2], b[2], Cin2, y[2], Cin3);
  12. full_adder1 a4(a[3], b[3], Cin3, y[3], Cout);
  13. endmodule
  14. module full_adder1
  15. (
  16. input wire a, b,
  17. input wire Cin,
  18. output wire y, Cout
  19. );
  20. assign y = a ^ b ^ Cin;
  21. assign Cout = (a & b) + (a & Cin) + (b & Cin);
  22. endmodule
  1. module tb_adder4();
  2. reg [3:0] a,b;
  3. reg Cin0;
  4. wire [3:0] y;
  5. wire Cout;
  6. initial begin
  7. a = 4'd5;
  8. Cin0 = 1'b1;
  9. b = 4'd8;
  10. #50 a = 4'd1;
  11. #50 a = 4'd3;
  12. #50 b = 4'd7;
  13. #50 a = 4'd10;
  14. end
  15. adder4_ripple ad
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