DDR3基本概念11 - DDR Read/Write training_dqs centering

DDR3基本概念11 - DDR Read/Write training

所谓的读或写训练，是为了保证：

1. 写操作时，时钟边沿对齐数据眼中心
2. 读操作时，DQS边沿对齐数据眼中心

Read training

Read Centering
The purpose of read centering is to train the internal read capture circuitry in the controller (or PHY) to capture the data in the center of the data eye. The memory controller (or PHY)
Enables bit 2 in mode register MR3 so that the DRAM returns data from the Multi Purpose Register (MPR) instead if the DRAM memory.
Then initiates a continuous stream of READs. The memory returns the pattern that was written in the previous MPR Pattern Write step. Let’s assume this pattern is an alternating 1-0-1-0-…
While the READs are going on, the internal read capture circuitry either increases of decreases an internal read delay register to find the left and right edge of the data eye.
When the edges of the eye are detected, the read delay registers are set appropriately to ensure the data is captured at the eye center.
The above steps are repeated for each of the DQ data bits

Write training

Write Centering
Similar to the read centering step, the purpose of write centering is to set the write delay for each data bit so that write data is centered on the corresponding write strobe edge at the DRAM device.
During write centering the PHY does the following WRITE-READ-SHIFT-COMPARE loop continuously
Initiates a continuous stream of WRITEs and READs
Incrementally changes write delay of the data bits
Compares the data read back to the data written
From the above loop the PHY can determine for what write-delay range it reads back good data, and hence it can figure out the left and write edges of the write-data eye. Using this dat,a the DQ is centered to the DQS for writes.

先这样，等空了再来补充完善。

参考文献

1. https://www.systemverilog.io/ddr4-initialization-and-calibration