Verilog专题（十三）计数器的级联实现1000分频的分频器_想要实现分频系数为1000的分频电路,须多个计数器级联。

作者：凡人多烦事01 | 2024-06-16 04:43:04

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想要实现分频系数为1000的分频电路,须多个计数器级联。

HDLBits网址：https://hdlbits.01xz.net/wiki/Main_Page

题目

From a 1000 Hz clock, derive a 1 Hz signal, called OneHertz, that could be used for the digital wall clock. Build the frequency divider using modulo-10 (BCD) counters and as few other gates as possible. Also output the enable signals from each of the BCD counters you use (c_enable[0] for the fastest counter, c_enable[2] for the slowest).

The following BCD counter is provided for you. Enable must be high for the counter to run. Reset is synchronous and set high to force the counter to zero. All counters in your circuit must directly use the same 1000 Hz signal.

我的设计

通过例化一个10进制bcd码计数器，来实现1000分频的分频器，即把一个1KHz的时钟通过分频的手段，变成一个1Hz的信号，那就计数到999给一个输出作为1Hz信号输出。

那怎么样计数到999？这个时候就要利用题目提供的BCD计数器，例化成为个位计数器、

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